1. Field of the Invention
The invention relates to memories made in integrated circuit form, especially but not exclusively electrically programmable non-volatile memories.
In large-capacity memories (having several tens of thousands of memory cells), it is the practice to improve manufacturing output by associating several redundancy columns (or lines) with the memory map. These redundancy lines or columns are designed to replace defective columns (or lines) of the memory maps. The following description shall be simplified by making reference only to columns, but it is also applicable to lines.
2. Description of the Prior Art
Integrated circuit memories, notably electrically programmable memories, are provided with redundancy means enabling the columns of defective cells to be repaired. The substitution of a redundancy column for a defective column should be transparent for the user, i.e. the user should be permitted to send an address corresponding to a defective column to the memory addressing input. The internal redundancy circuitry then takes over the task of neutralizing the defective column and of reading or writing a piece of information in a cell of a replacement column, instead of attempting to read or to write it in a cell of the defective column.
This transparency makes it necessary to place the following circuits at the input of the memory: defective address recognition circuits, deselection circuits to neutralize the defective columns, and routing circuits for routing towards the replacement columns.
All these circuits therefore substantially modify the initial decoding of the memory addresses. This decoding consists in associating a determined column with a determined input address.
Now, it so happens that, outside the normal mode of use of the memories (in which a user can read and write with complete transparency if redundant columns have been put into service), a second mode exists which is the test mode.
Indeed, it is necessary for all the memory cells to be tested before the circuit is declared worthy of being marketed. In particular, the test consists in programming all of the cells from their initial state (blank or virgin state) to a programmed state, and in ascertaining that they are correctly programmed. In fact, it is generally during this test that the defective columns are detected and that the replacement columns are put into service.
It may take some milliseconds to test a memory cell. However, integrated circuits are manufactured in batches, and each batch comprises tens of silicon wafers, each bearing several tens of chips, and each of these chips themselves bear several tens or hundreds of thousands of memory cells. The testing operations may therefore take a considerable amount of time since all the cells have to be methodically tested.
To reduce this testing time, it has been proposed that the cells be programmed according to a pattern (for example a chequerboard pattern) that enables the simultaneous programming of several columns of memory cells. In other words, in the testing mode, instead of writing individually in one column and then in another etc., an element of information is written simultaneously in parallel in several columns at a time, for example in 2 or 4 or 8 columns at a time. The testing time is correspondingly divided.
The term "grouped test" can be hereafter applied to this test mode in which several columns are programmed at a time.
According to the invention, it has been observed that it is not possible, in existing memories, to carry out a grouped test twice in succession although it is quite possible that such a test might be necessary under certain circumstances.
For example, the testing of an entire batch has to be recommenced if a false manoeuvre has been made during the testing of the batch or, furthermore, if the tester has broken down and if the malfunction has not been detected soon enough, etc.
Moreover the "grouped" test cannot be applied to batches having already been tested: indeed, redundancy columns have been (irreversibly) put into service in certain chips, and this putting into service is accompanied by major modifications in the internal addressing of the memory. Yet, the "grouped" test mode also calls for a modification in the internal addressing of the memory since it requires the simultaneous addressing of several columns.
It has been realized that the addressing modifications due to the putting into service of the redundancy columns were, in practice, incompatible with the addressing modifications required to carry out a grouped test mode. Therefore, it has not been possible to carry out a grouped test a second time, if the first test has led to replacement columns being put into service.